1. Field of the Invention
The present invention relates to a multiport memory which includes a plurality of groups of bit lines, extending in the direction of a column within each memory cell, and which can access different memory cells in parallel.
2. Description of the Related Art
There is a semiconductor memory called a "multiport memory" which can access different memory cells in parallel. The method of accessing different memory cells in parallel can be a method in which there are two input ports for an address signal and an input/output port for a data signal and writing or/and reading can be performed on different memory cells in parallel, a method in which one and is used exclusively for writing and the other port is used exclusively for reading, and a method in which writing and reading can be carried out through one port, and the other port is used exclusively for reading. In the latter case, it is impossible to access the same memory cell concurrently. Moreover, there is a method in which one input port is provided for an address signal and reading written data items car be carried out in parallel with writing the data to the memory cell indicated by the address signal. In any of the modes, bit lines extending in the direction of a column within each memory cell are grouped into a plurality of independent subgroups.
However, such an array causes parasitic capacitance to develop between adjoining bit lines. Because the capacity of a multiport memory has grown in recent years, the capacitance of the parasitic capacitor has increased and the adverse effect thereof cannot be ignored any longer. The adverse effect becomes critical when memory cells on the same column are accessed in parallel through different ports. These accesses can cause a malfunction. Assuming that the operating speed of a memory is low, and that a sense amplifier is actuated for amplification after the potential on a read data line varies sufficiently due to reading of data from a memory cell, the adverse affect on an adjacent bit line (write data line or read data line) due to parasitic capacitance is so small as not to pose a problem. However, there is a demand for a multiport memory offering a high operating speed, or especially, a high reading speed. For improving the operating speed, the adverse effect of the parasitic capacitance cannot be ignored.
Moreover, in the conventional device, when a memory cell is constituted by a flip-flop (FF), the device is a volatile memory device whose stored data is lost when the power supply is turned off. A non-volatile multiport memory having memory cells accessible in parallel, a type offering a high operating speed and having a simple configuration is required.